1. Field of the Invention
The present invention relates to transistor arrays, and more particularly, to transistor arrays arranged in consideration of error value on a single chip.
2. Description of Related Art
A layout method for a conventional transistor array is explained below with reference to an examplary transistor array of a flash type digital to analog (“D/A”) converting circuit that receives an 8-bit digital signal and converts it to generate an analog signal having 256 various levels.
FIG. 1 shows a configuration of a conventional digital to analog converting circuit. The D/A converting circuit of FIG. 1 includes four-to-fifteen type converters 10-1 and 10-2, an MSB transistor array 20-1, an LSB transistor array 20-2, MSB switches 30-1, and LSB switches 30-2.
As shown in FIG. 1, the MSB transistor array 20-1 includes transistors M1 to M15, and the LSB transistor array 20-2 includes transistors L1 to L15. The size of each of the transistors M1 to M15 of the MSB transistor array 20-1 is 16 times as large as that of each of the transistors L1 to L15 of the LSB transistor array 20-2. That is, 16 LSB-sized transistors constitute a single MSB transistor. Each of the transistors M1 to M15 and L1 to L15 includes an NMOS transistor having a drain to which a power voltage VCC is applied, and a gate to which a bias voltage is applied. The MSB switches 30-1 include switches MS1 to MS15 connected between the respective transistors M1 to M15 and a terminal for generating an output signal Aout, and the LSB switches 30-2 include switches LS1 to LS15 connected between the respective transistors L1 to L15 and the terminal for generating the output signal Aout.
Operation of the components of the D/A converting circuit of FIG. 1 is explained below.
The four-to-fifteen type converter 10-1 converts an upper 4-bits B8 to B5 of an 8-bit digital signal B8 to B1 to generate a 15-bit digital signal MO1 to MO15. When the upper 4-bits B8 to B5 are “0000”, the digital signal MO1 to MO15 of “00 . . . 0” is generated. And, when the upper 4-bits B8 to B5 are “0001”, the digital signal MO1 to MO15 of “00 . . . 1” is generated. Also, when the digital signal B8 to B5 is “0011”, the digital signal MO1 to MO15 of “00 . . . 011” is generated. That is, whenever the digital signal B8 to B5 is increased by 1, a bit number of “1” of the digital signal MO1 to MO15 is increased by 1. The four-to-fifteen type converter 10-2 converts a lower 4-bits B4 to B1 of an 8-bit digital signal B8 to B1 to generate a 15-bit digital signal LO1 to LO15. The transistors M1 to M15 allow a constant amount of electric current to flow, and the transistors L1 to L15 also allow a constant amount of electric current to flow. Here, since a size of each of the transistors M1 to M15 is 16 times as large as that of each of the transistors L1 to L15, an amount of electric current flowing along each of the transistors M1 to M15 is 16 times as much as that flowing along each of the transistors L1 to L15. The MSB switches MS1 to MS15 are each turned on when each of the digital signals MO1 to MO15, respectively, have a high level, allowing an electric current to flow to the terminal for generating the output signal Aout. The LSB switches LS1 to LS15 are each turned on when each of the digital signals LO1 to LO15, respectively, have a high level, allowing an electric current to flow to the terminal for generating the output signal Aout. An electric current through the MSB switches 30-1 and an electric current through the LSB switches 30-2 join and flow to the terminal for generating the output signal Aout. A current outputted through the terminal for generating the output signal Aout has a total of 256 levels. At this time, a difference between current levels should be uniform.
However, in the conventional layout method of the MSB and LSB transistor array, analog signals outputted from the output signal (Aout) generating terminal do not have a uniform level difference.
FIG. 2 shows an example of a layout method of the MSB and LSB transistor array of the flash type D/A converting circuit of FIG. 1. In FIG. 2, the transistor array has 16 rows and 16 columns.
In FIG. 2, T1,1 to Tn,n denote an array area. A digit next to “T” denotes a row, and a next digit denotes a column. For example, T1,1 denotes an array area located at a first row and a first column.
A layout method of the transistor array of FIG. 2 is explained below.
The MSB transistor M1 is arranged on each of the areas T1,1, T2,1, . . . , T16,1, which are each the same size as an LSB transistor. The MSB transistor M2 is arranged on each of the areas T2,2, . . . , T16,2 and T1,2, which are each the same size as an LSB transistor. The MSB transistor M15 is arranged on each of the areas T2,15, . . . , T16,15 and T1,15, which are each the same size as an LSB transistor. 16 transistors which constitute each of the MSB transistors M1 to M15 are arranged in the same column, forming a line. The LSB transistors L1 to L15 are, respectively, arranged on the areas T2,16, . . . , T15,16, and T1,16. Thus, the LSB transistors L1 to L15 are arranged in a 16th column, forming a line.
The layout method of FIG. 2 has a problem in that transistors of the transistor array do not have the same operational characteristics since the transistors of the transistor array have different temperature distributions and process variations according to their arranged location. That is, the transistors of the transistor array have an error value that varies with a temperature distribution and a process variation. Therefore, signals outputted from the transistor array could not be generated to have a uniform level difference.
FIG. 3 shows another layout method of the MSB and LSB transistor array of the flash type D/A converting circuit of FIG. 1. As shown in FIG. 3, a single transistor is arranged on each of the array areas T1,1 to T16,15.
The layout method of FIG. 3 is explained below.
The LSB transistors L1 to L15 are arranged on the areas T1,8, T2,8, . . . , T15,8 and T16,8, respectively. That is, the LSB transistors L1 to L15 are arranged in the 8th column, forming a line. The MSB transistor M1 is arranged on each of the areas T1,1, . . . T7,7, T9,9, . . . , T15,15, and T16,1, which are each the same size as an LSB transistor. The MSB transistor M2 is arranged on each of the areas T1,15, T2,1, . . . , T8,7, T10,9 . . . , T16,15, which are each the same size as an LSB transistor. The MSB transistor M15 is arranged on each of the areas T1,2, . . . , T6,7, T8,9. T14,15, T15,1, and T16,2, which are each the same size as an LSB transistor. In the same way, the rest of the MSB transistors M3 to M14 are also arranged in a diagonal direction. That is, the MSB transistors M1 to M15 are arranged in the areas along diagonal directions while skipping the 8th column.
The layout methods of FIGS. 2 and 3 are described in U.S. Pat. No. 5,568,145.
To solve a problem of the layout method of FIG. 2, the layout method of FIG. 3 arranges each of the MSB transistors M1 to M15, which are turned on simultaneously, in a diagonal direction to reduce the effects of temperature distribution and process variation.
However, since the LSB transistors L1 to L15 are arranged only in a central portion, such arrangement cannot remove the effects of temperature distribution and process variation. Therefore, signals outputted from the transistor array can not be generated with a uniform level difference.